The present invention relates to a driver circuit for driving a variety of loads, such as capacitive loads or inductive loads, and a driver integrated circuit (hereinafter referred to as the "driver IC") having the driver circuit therein. The present invention further relates to a display device and an electronic device driven by the driver circuit and the driver IC.
In recent years, semiconductor integrated circuits or driver ICs have been developed in which there is packaged either a circuit for driving a capacitive load, such as a flat display, e.g., a gas discharge display panel (or plasma display panel) or an electroluminescence display panel (or EL display panel), or a circuit for driving an inductive load, such as an electric motor. Since in these driver circuits a relatively high voltage of 100 V to several hundreds of volts are handled, the power consumption of the driver circuit has to be reduced so that it may be integrated in a semiconductor chip.
First, a conventional example of an output driver circuit section in the driver circuit will be described.
In order to effect a display on a flat display panel, there has been used in the prior art a driver circuit, as shown in FIG. 1 of Japanese Patent Laid-Open No. 15327/1984. When a lower bipolar transistor in the circuit is turned on, a load current flows in and through a diode which is provided in the forward direction between the base terminal and emitter terminal of a bipolar transistor arranged on the upper side. Since the base and emitter of the bipolar transistor are reversely biased, the upper bipolar transistor is turned off. When the lower bipolar transistor is off, on the other hand, the upper bipolar transistor is turned on because the power source is connected through a resistor to the base terminal of the upper bipolar transistor. This circuit makes it possible to drive the display of the panel with a simple circuit construction.
On the other hand, a driver circuit, as shown in FIG. 3 of Japanese Patent Laid-Open No. 15327/1984 or in FIG. 3 of Japanese Patent Laid-Open No. 15328/1984, is designed to improve the shape of the output waveform and to reduce the power consumption. However, this circuit has a construction using more elements than those of the above-described circuit.
According to the prior art, the driver circuit, as shown in FIG. 1 of Japanese Patent Laid-Open No. 15327/1984, is advantageous in that a smaller number of elements are used, but involves a problem in that, during a low output time, namely, while the lower transistor is on, the power consumed by a resistor for driving the base of the upper transistor is high.
This high power consumption raises a critical problem especially in circuits required to operate at a high speed, circuits of multi-channel outputs and circuits in which the on period of the lower transistor is long. Another problem is the difficulty in the mounting of parts monolithically, because of high heat generation.
These problems will be described in more detail below.
The first problem is the increase of the current consumed when the operation of the circuit is speeded up.
For a higher speed of a high output of the circuit, it is necessary to enhance the current carrying ability of a transistor Q1 thereby to shorten the time period taken to change the capacity of the circuit by reducing the resistance of a resistor for driving the base of the transistor Q1. This reduction in the resistance raises a problem involving an increase of the current drawn from a high-voltage power source at the low output time when the lower transistor Q2 is on.
The second problem is that the current consumption is multiplied according to the number of outputs, in the case of a driving operation in which these outputs are simultaneously set low. For driving the scanning lines of a plasma display panel, for example, there is not only the general scanning type drive (hereinafter referred to as the "scanning drive" in which the scanning lines are selectively scanned sequentially one by one from the highest to the lowest ones so that the selected scanning lines are set low while the unselected lines are set high), but also the drive for setting all lines simultaneously high or low. The number of scanning lines is as many as 480 to 1,024, depending upon the resolution of the panel.
Let the case be considered in which the circuit described above is used for driving the scanning lines of a plasma display panel.
Since more than two-channel outputs simultaneously do not become low for the scanning drive period, the current flowing through a base driving resistor for one channel becomes the object, and the current consumption hardly raises a problem for this drive period. During the drive period where all the lines are high, the transistor Q2 (the lower transistor) is off so that little current flows through the transistor Q2. During the period where all the lines are low-driven, on the other hand, the transistor Q2 is turned on so that the base current of the transistor Q1 flows from the high-voltage power source, and a current corresponding to the total number of scanning lines flows in the entirety of the panel.
An example of this problem will be considered for the case of driving 480 scanning lines in the load drive circuit, assuming that the high-voltage power source is 150 V, the current flowing through the resistor when the lower transistor is on is 10 mA for each channel, and the duty when all the outputs are low is 50%, for example. The problem is that the current flowing through the resistor for the all-low period is as high as 10 (mA).times.480 (channels)=4.8 (A). Moreover, the power loss is as high as 4.8 (A).times.150 (V).times.50 (%)=360 (W), raising a major problem in the system, and it is difficult to release the heat when the drive circuit is integrated.
The driver circuit shown in FIG. 3 of Japanese Patent Laid-Open No. 15327/1984 or in FIG. 3 of Japanese Patent Laid-Open No. 15328/1084, can solve the aforementioned problems of the prior art, but requires a construction using many elements. Since this circuit requires multiple channels, for example, as many in a 480 to 1,024 as driver circuit for a flat panel display, the integration of this driver circuit leads to an increase in the semiconductor chip area, raising the cost.
An example of a conventional level shift circuit section in the driver circuit now will be described.
As a level shift circuit for a high-voltage driver, there is a known circuit which is composed of two high breakdown voltage NMOSs and two high breakdown voltage PMOSs, the drains of which are connected with the gates of the other devices. The circuit construction of this driver IC is shown in FIG. 21. This driver IC is provided with level shift circuits 100 and output driver circuits 200, the number of which is equal to the number of outputs of the driver IC (64 or 128 outputs).
As another level shift circuit for the high-voltage driver IC of the prior art, there is a known circuit which uses a constant current source composed of a resistor and an NMOS switch, as shown in FIG. 22.
In the high-voltage driver IC (in which a high-voltage power source HV has a voltage as high as several tens V or more, for example) of FIG. 21, the voltage of the high-voltage power source HV is applied as it is between the gates and sources of level shifting PMOSs P1 and P2 and a PMOS P3 of the output driver section. This makes it necessary for the gate oxide films of the PMOSs P1 to P3 to be sufficiently thick for preventing current leakage and dielectric breakdown even when the voltage of the high-voltage power from source HV is applied. This necessity complicates the channel structure, making it difficult to produce the MOS transistors. When the high-voltage power source HV has a voltage of 150 V or higher, moreover, the gate oxide film thickness has to be no less than 0.6 microns from the point of view of reliability, and this thickness is equal to or more than that of the LOCOS (Local Oxidation of Silicon) oxide film, thus raising a problem that the elements are hard to separate.
In the arrangement of FIG. 22, the voltage of the high-voltage power source HV is not applied between the gates and sources of the MOS transistors. When the output voltage is high, however, an NMOS switch N1 in series with a resistor R1 is on so that a through current flows from the high-voltage power source HV to a low-voltage power source VSS through the resistor R1 and the NMOS switch N1. This through current increases when all the outputs are at the high level, and the resistance has to be raised to prevent the flow of the through current. However, an excessively high resistance raises a problem that the operating speed of the level shift circuit is lowered and the layout area is increased.
An object of the present invention is to reduce the power consumption and the current consumption of a driver circuit and a driver IC.